Method and related apparatus for controlling a peripheral device to transfer data to a bus

ABSTRACT

A method and related apparatus used for controlling a peripheral device to transfer data to a bus. The peripheral device has a bus interface circuit and a controller. The method includes storing data outputted from the controller into a first storage block of the bus interface circuit, utilizing the bus interface circuit to simultaneously control the first storage block to output its stored data to the bus and control a second storage block of the bus interface circuit to store data outputted from the controller, and utilizing the bus interface circuit to control the second storage block to output its stored data to the bus.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of applicant's earlier application,Ser. No. 10/707,806, filed Jan. 14, 2004, which itself claims thebenefit of U.S. Provisional Application No. 60/458,011, which was filedon Mar. 28, 2003, both applications hereby being incorporated byreference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method and a related apparatus forcontrolling data transmission. In particular, the present inventiondiscloses a method and a related apparatus for controlling a peripheraldevice to transfer data to a bus.

2. Description of the Prior Art

Generally speaking, a computer system has a plurality of electroniccomponents. In addition, the computer system also has many buses usedfor delivering data outputted from one electronic component to otherelectronic components. In other words, the buses establish connectionsamong the electronic components installed on the computer system. Pleaserefer to FIG. 1, which is a diagram of a prior art computer system 10.The computer system 10 comprises a central processing unit (CPU) 12, anorth bridge circuit 14, a south bridge circuit 16, a PCI bus 18, adisplay controller 20, a memory 22, a small computer system interface(SCSI) controller 24, a hard-disk drive 26, a network controller 28, andan audio controller 30. The CPU 12 is used for controlling overalloperations of the computer system 10. The north bridge circuit 14 isused for arbitrating signal transmission between high-speed peripheraldevices (the display controller 20 and the memory 22 for example) andthe CPU 12. However, the south bridge circuit 16 is used for arbitratingsignal transmission between low-speed peripheral devices (the hard-diskdrive 26, the network controller 28, and the audio controller 30 forexample) and the north bridge circuit 14. As mentioned above, the PCIbus 18 on the computer system 10 is used for establishing connectionsamong peripheral devices.

The display controller 20 is used for driving an external display devicesuch as a monitor through video signals. The memory 22 is a volatilestorage device for storing volatile data. The SCSI controller 24functions as a bridge used for controlling signal transmission betweenthe PCI bus 18 and a device (the hard-disk drive 26 for instance)connected to the SCSI controller 24. It is well-known that the hard-diskdrive 26 is a non-volatile storage device for storing non-volatile data.The network controller 28 such as a network interface card (NIC) is usedfor controlling data transmission between the computer system 10 and anexternal network. The audio controller 30 such as an audio card is usedfor performing signal conversion between digital audio signals andanalog audio signals. That is, the audio controller 30 is capable ofconverting digital audio signals into corresponding analog audio signalsfor driving a speaker, and is also capable of converting analog audiosignals inputted by a microphone into corresponding digital audiosignals.

As mentioned above, the peripheral devices such as the networkcontroller 28, the audio controller 30, and the hard-disk drive 26 haveto utilize the PCI bus 18 to transfer data to the memory 22 or the CPU12 through the north bridge circuit 14 and the south bridge circuit 16.Therefore, how to efficiently utilize the PCI bus 18 to deliver massivedata has become an important issue.

SUMMARY OF THE INVENTION

This invention provides a method and a related apparatus for controllinga peripheral device to transfer data to a bus.

Briefly summarized, the preferred embodiment of the present inventionprovides a method of controlling data outputted from a peripheraldevice. The peripheral device is installed on a computer system, and theperipheral device comprises a bus interface circuit and a controller.The bus interface circuit is electrically connected to a bus of thecomputer system for controlling data transmission between the peripheraldevice and the bus, and the controller is electrically connected to thebus interface circuit. The method includes positioning at least a firststorage block and a second storage block in the bus interface circuit,storing data outputted from the controller in the first storage block,utilizing the bus interface circuit for simultaneously controlling thefirst storage block to transfer data within the first storage block tothe bus and controlling the second storage block to store data outputtedfrom the controller, and utilizing the bus interface circuit to controlthe second storage block to transfer data within the second storageblock to the bus.

It is an advantage of the present invention that a plurality of buffersare alternatively used for storing source data waiting to be deliveredto a target device. A data transfer rate between a controller and a businterface circuit cannot be less than a data transfer rate between thebus interface circuit and an external bus. Therefore, before all of thesource data are completely transferred to the external bus, the claimedperipheral device is capable of continuously occupying the external buswithout entering a waiting state. In addition, the implemented buffer ofthe claimed peripheral device has a small capacity. Therefore, theproduction cost of the buffers is reduced, and the chip size of the businterface circuit is greatly shrunk. Moreover, the data transferefficiency is also improved because the claimed peripheral device isblocked from entering the waiting state.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a prior art computer system.

FIG. 2 is a block diagram of a peripheral device according to thepresent invention.

FIG. 3 is a timing diagram of the peripheral device shown in FIG. 2.

FIG. 4 is a block diagram of a peripheral device according to anotherembodiment of the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 2, which is a block diagram of a peripheral device50 according to the present invention. The peripheral device 50 includesa controller 52 and a bus interface circuit 54. The controller 52 is akernel hardware component of the peripheral device, and is used forperforming and controlling main functionality of the peripheral device50. The bus interface circuit 54 is electrically connected to acorresponding bus 56, and functions as an input/output interface of theperipheral device 50. In addition, the bus interface circuit 54 has twobuffers 58, 60 and two switches 62 a, 62 b. The peripheral device 50according to the present invention is applied on the computer system 10shown in FIG. 1, and is capable of being connected to any bus of thecomputer system 50. For instance, the peripheral device 50 can beconnected to the PCI bus 18 shown in FIG. 1, the prior art industrystandard architecture (ISA) bus, or the PCIX bus recently designed forhigh-speed data transmission. The peripheral device 50 can be anydata-retrieving device such as an optical disk drive (not shown) or thenetwork controller 28 shown in FIG. 1, the audio controller 30 shown inFIG. 1, or the hard-disk drive 26 shown in FIG. 1. In addition, the businterface circuit 54 also can function as an SCSI interface. Forexample, the hard-disk drive 26 shown in FIG. 1 is connected to the SCSIcontroller 24 through the SCSI interface, and then accesses the PCI bus18 for receiving and delivering data. Similarly, the bus interfacecircuit 54 can also function as a USB interface or an IEEE 1394interface, and the PCI bus 18 shown in FIG. 1 can be accessed through aUSB controller or an IEEE 1394 controller. In the preferred embodiment,the buffers 58, 60 operate according to a well-known first-in-first-out(FIFO) storage mechanism. That is, the data first pushed into thebuffers 58, 60 are first popped out of the buffers 58, 60.

The switch 62 a is used for determining which one of the buffers 58, 60is electrically connected to the bus 56. When the buffer 58 issuccessfully connected to the bus 56, data stored in the buffer 56 canbe passed to the bus 56. Similarly, when the buffer 60 is successfullyconnected to the bus 56, data stored in the buffer 60 can be passed tothe bus 56. The switch 62 b is used for controlling which one of thebuffers 58, 60 is electrically connected to the controller 52.Therefore, when the controller 52 is successfully connected to thebuffer 58 through the switch 62 b, the controller 52 is capable ofoutputting data to the buffer 58 and storing data into the buffer 58.Similarly, when the controller 52 is successfully connected to thebuffer 60 through the switch 62 b, the controller 52 is capable ofoutputting data to the buffer 60 and storing data into the buffer 60.

Please refer to FIG. 3, which is a timing diagram of the peripheraldevice 50 shown in FIG. 2. The horizontal axes listed from top to bottomcorrespond to a clock signal Clock, a control signal START, aninformation signal LEN, a control signal WRDY, a control signal WAVL,output data WDATA, and time Time. Suppose that each of the buffers 58,60 has an identical capacity of 8 DWs, and the controller 52 wants topass 20 DWs to a target device. For example, the peripheral device 50 isa network controller 28 shown in FIG. 1, and the target device is thememory 22 shown in FIG. 1. Therefore, the peripheral device 50 has todeliver data to the bus 56 (the PCI bus 18 shown in FIG. 1 for example)first, and then data are transferred to the target device with the helpof the bus 56.

As mentioned above, the bus interface circuit 54 provides aninput/output interface between the peripheral device 50 and the bus 56so that the peripheral device 50 is capable of outputting data to thebus 56. In other words, the controller 52 first stores data into thebuffers 58, 60 of the bus interface circuit 54. At time t1, thecontroller 52 outputs a control signal START to the bus interfacecircuit 54 for starting the data transaction between the controller 52and the bus interface circuit 54. At the same time, the controller 52also transfers an information signal LEN, which records the data lengthinformation LI, to the bus interface circuit 54 for informing the businterface circuit of the amount of data involved in the datatransaction. In the preferred embodiment, because the controller 52wants to pass the data having 20 DWs to another device, the data lengthinformation LI is used to indicate that the amount of transmitted datacontains 20 DWs.

In the beginning, the buffers 58, 60 are empty. Therefore, the businterface circuit 54 outputs a control signal WAVL corresponding to thehigh logic level for informing the controller 52 that the buffers 58, 60are capable of receiving data. At time t4, the controller 52 outputs acontrol signal WRDY corresponding to the high logic level to command thebus interface circuit 54 to start receiving data.

Suppose that the controller 52 can output two DWs to buffers 58, 60during one period of the clock signal Clock, and each of the buffers 58,60 can output one DWs to the bus 56 during one period of the clocksignal Clock. In other words, the data transfer rate between thecontroller 52 and the bus interface circuit 54 is not less than the datatransfer rate between the bus interface circuit 54 and the bus 56. Themain purpose is to prevent the peripheral device 50 from entering awaiting state before the data transaction is completed. The detailedprinciple of the claimed mechanism is explained later.

When the control signal WRDY has a transition from the low logic levelto the high logic level at time t4, the bus interface circuit 54controls the switch 62 b to select either the buffer 58 or the buffer 60for storing data outputted from the controller 52. For example, theswitch 62 b is controlled to connect the buffer 58 and the controller 52first. Therefore, the buffer 58 with a capacity of 8 DWs continuouslyreceives 8 DWs outputted from the controller 52 within a duration t4-t8.Please note that the buffer 58 is full at time t8, but another buffer 60is still empty to be capable of storing 8 DWs. Therefore, after theperipheral device 50 occupies the bus 56 to deliver data, the businterface circuit 54 controls the switch 62 a to connect the buffer 58and the bus 56, and drives the buffer 58 to transfer its stored data (8DWs) to the bus 56. At time t8, the controller 52 simultaneouslycommands the switch 62 b to connect the buffer 60 and the controller 52because controller 52 does not deliver all of the source data (20 DWs)to the bus interface circuit 54 yet. That is, the buffer 60 is furtherenabled to store data outputted from the controller 52.

Similarly, the buffer 60 has a capacity of 8 DWs. Therefore, thecontroller 52 needs 4 periods of the clock signal Clock to load thebuffer 60 with 8 DWs. That is, the data transaction between thecontroller 52 and the buffer 60 is activated within a duration t8-t12.As mentioned above, each of the buffers 58, 60 is capable of outputtingone DW only to the bus 56 during one period of the clock signal Clock.Therefore, the buffer 58 merely outputs 4 DWs during a duration t8-t12.At time t12, the buffer 58 still has 4 DWs so that all of its storeddata are not completely transferred to the bus 56 yet. In other words,both of the buffers 58, 60 are unable to receive data after t12. Then,the bus interface circuit 54 resets the control signal WAVL at t12 toinform the controller 52 that the buffers 58, 60 cannot be used forstoring data now.

It is obvious that the buffer 58 successfully transfers all of itsstored data to the bus 56 at t16. That is, the buffer 58 outputs 8 DWswithin the duration t8-t18. Because the buffer 58 is empty now, thebuffer 58 can be used for storing data transmitted from the controller52. Therefore, the bus interface circuit 54 triggers the control signalWAVL at t16 so that the control signal WAVL has a transition from thelow logic level to the high logic level for informing the controller 52that it can continue outputting remaining data to the bus interfacecircuit 54. The controller 52 has to control the switch 62 b to connectthe buffer 58 and the controller 52 for utilizing the buffer 58 toreceive data that are transferred from the controller 52 to the businterface circuit 54. At the same time, the bus interface circuit 54controls the switch 62 a to connect the buffer 60 and the bus 56, anddrives the buffer 60 to start outputting its stored data. Within theduration t4-t12, the controller 52 has transferred 16 DWs to the businterface circuit 54. However, controller 52 actually wants to pass 20DWs to another device through the bus 56. Therefore, the controller 52needs to spend two periods of the clock signal Clock for outputting theremaining 4 DWs.

As shown in FIG. 6, the buffer 58 successfully stores 4 DWs at t18, andthe data transaction between the controller 52 and the bus interfacecircuit 54 is completed. Therefore, the controller 52 resets the controlsignal WRDY at t18 so that the control signal WRDY has a transition fromthe high logic level to the low logic level for informing the businterface circuit 54 that the data transaction is finished. Then, afterthe buffer 60 finishes outputting 8 DWs to the bus 56, the bus interfacecircuit 54 controls the switch 62 a to connect the buffer 58 and the bus56 for outputting remaining 4 DWs currently stored in the buffer 58 tothe bus 56. In other words, after the buffer 60 completes outputting itsstored data to the bus 56 within 8 periods of the clock signal Clock,the bus interface circuit 54 continues controlling the buffer 58 tooutput remaining data stored in the buffer 58 to the bus 56 within 2periods of the clock signal Clock.

When the buffer 60 receives data outputted from the controller 52 withinthe duration t8-t12, the buffer 58 simultaneously outputs its storeddata to the bus 56. As mentioned before, the data transfer rate betweenthe controller 52 and the bus interface circuit 54 is not less than thedata transfer rate between the bus interface circuit 54 and the bus 56.Therefore, the buffer 58 does not output all of its stored data to thebus 56 before the buffer 60 is full. In other words, when the buffer 60is full, the peripheral device 50 does not release the bus 56 becausethe buffer 58 is still outputting stored data through the bus 56. In thepreferred embodiment, the peripheral device 50 does not enter thewaiting state before the data transaction is finished. On the contrary,suppose that the data transfer rate between the controller 52 and thebus interface circuit 54 is less than the data transfer rate between thebus interface circuit 54 and the bus 56. Therefore, the buffer 58outputs all of its stored data before the buffer 60 is fully loaded withdata outputted from the controller 52. That is, the buffer 58 is empty,and the buffer 60 is not full yet.

It is well-known that the bus interface circuit 54 does not control thebuffer 60 to output its stored data because the buffer 60 is not full.Therefore, before the buffer 60 is fully loaded with data, theperipheral device 50 has to enter the waiting state because the buffer60 is unable to output its stored data. Other devices connected to thebus 56 have the chance to take over the bus 56 originally occupied bythe peripheral device 50. In other words, when the buffer 60 of theperipheral device 50 stores 8 DWs after a period of time, the peripheraldevice 50 needs to wait until the bus 56 is available to the peripheraldevice 50.

After taking control of the bus 56 again, the peripheral device 50 thenis capable of outputting the data stored in the buffer 60. From theabove description, the data transfer rate between the controller 52 andthe bus interface circuit 54 cannot be less than the data transfer ratebetween the bus interface circuit 54 and the bus 56. Therefore, whilethe controller 52 is outputting data to another device, the peripheraldevice 50 does not enter the waiting state, and is capable of utilizingthe bus 56 continuously for completing the overall data delivery.

In the preferred embodiment, the buffer 58 and the buffer 60 has thesame capacity. However, the buffers 58, 60 with different capacities canbe implemented on the peripheral device 50 as well. For example, supposethat the capacity of the buffer 60 is twice as big as the capacity ofthe buffer 58. The period of time needed to drive the buffer 60 to havea full capacity is certainly less than the period of time needed toempty the buffer 58 originally having a full capacity as long as thedata transfer rate between the controller 52 and the bus interfacecircuit 54 at least doubles the data transfer rate between the businterface circuit 54 and the bus 56. In other words, when the peripheraldevice 50 utilizes the bus 56 to deliver data, the peripheral device 50has better data processing performance because it does not enter thewaiting state.

In order to prevent the peripheral device 50 from entering the waitingstate, the preferred embodiment has to adequately determine capacitiesof the buffers 58, 60 according to the transfer rate between thecontroller 52 and the bus interface circuit 54 and the data transferrate between the bus interface circuit 54 and the bus 56. In addition,the bus interface circuit 54 in the preferred embodiment only has twobuffers 58, 60. However, a plurality of buffers can be applied on thebus interface circuit 54 to complete the data transaction. Please referto FIG. 4, which is a block diagram of a peripheral device 150 accordingto another embodiment of the present invention. Differing from theperipheral device 50 shown in FIG. 2, the peripheral device 1 50 has abus interface circuit 154 containing three buffers 58, 59, 60. All otherfeatures are the same, and the same components are indicated by the samereference numbers. Based on the above-mentioned operations, the businterface circuit 54 successively activates these buffers 58, 59, 60 tostore data delivered from the controller 52.

In the beginning, the bus interface circuit 54 enables the buffer 58 tostore data outputted from the controller 52 until the buffer 58 is full.After the peripheral device 50 occupies the bus 56 successfully, the businterface circuit 54 drives the buffer 58 to start outputting data tothe bus 56, and simultaneously enables the buffer 59 to continuouslyreceive data outputted from the controller 52. As mentioned above, thetiming when the buffer 59 is fully loaded with data needs to be prior tothe timing when the buffer 58 outputs all of its stored data for thesake of preventing the peripheral device 50 from entering the waitingstate. That is, before the buffer 58 completes outputting all of itsstored data, the buffer 59 must be fully loaded with data. When thebuffer 59 is full, the remaining buffer 60 is still empty. Therefore,the bus interface circuit 54 can drive the buffer 60 to start receivingdata outputted from the controller 52.

When the buffer 58 completes outputting all of its stored data, the businterface circuit 54 drives the buffer 59, whose capacity is full, tostart outputting its stored data. Similarly, the timing when the buffer60 is fully loaded with data needs to be prior to the timing when thebuffer 59 outputs all of its stored data for the sake of preventing theperipheral device 50 from entering the waiting state. That is, beforethe buffer 59 completes outputting all of its stored data, the buffer 60needs to be fully loaded with data. When the buffer 60 is full, theavailable buffer 58 is empty. Therefore, the bus interface circuit 54can drive the buffer 58 to start receiving data outputted from thecontroller 52. When the buffer 59 completes outputting all of its storeddata, the bus interface circuit 54 drives the buffer 60, whose capacityis full, to start outputting stored data. The identical operationsmentioned above are repeated, and the buffers A, B, C can be used forreceiving data delivered from the controller 52 and outputting storeddata to the bus 56 sequentially. In the end, the same objective ofoutputting data to the bus 56 through the peripheral device 50 isachieved.

The claimed method of controlling data outputted from the claimedperipheral device utilizes a plurality of buffers for alternativelystoring source data waiting to be delivered to a target device.Concerning the claimed peripheral device, a data transfer rate between acontroller and a bus interface circuit cannot be less than a datatransfer rate between the bus interface circuit and an external bus.Therefore, before all of the source data are completely transferred tothe external bus, the claimed peripheral device is capable ofcontinuously occupying the external bus without entering a waitingstate. In addition, the implemented buffer of the claimed peripheraldevice has a small capacity (64 DWs for example). The production cost ofthe buffers is reduced, and the chip size of the bus interface circuitis greatly shrunk. Moreover, the data transfer efficiency is alsoimproved because the claimed peripheral device is blocked from enteringthe waiting state during the data transmission.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A method of controlling data outputted from a peripheral device, theperipheral device being installed on a computer system, the peripheraldevice comprising a bus interface circuit and a controller, the businterface circuit comprising a plurality of storage blocks and beingelectrically connected to a bus of the computer system for controllingdata transmission between the peripheral device and the bus, thecontroller being electrically connected to the bus interface circuit,the method comprising: storing data outputted from the controller to afirst storage block; and transferring the stored data from the firststorage block to the bus and simultaneously storing data outputted fromthe controller to other storage blocks; wherein the data transfer ratebetween the controller and the bus interface circuit is not less thanthe data transfer rate between the bus interface circuit and the bus. 2.A computer system comprising: a bus; a bus interface electricallyconnected to the bus, the bus interface having a plurality of storageblocks; and a controller electrically connected to the bus interface forsimultaneously controlling the transfer of stored data from a firststorage block to the bus and storing data from the controller to otherstorage blocks; wherein the data transfer rate between the controllerand the bus interface is not less than the data transfer rate betweenthe bus interface and the bus.
 3. The computer system of claim 2 whereinthe bus interface further comprises: a first switch electricallyconnected between the bus and the storage blocks for selectivelyconnecting the bus to one of the storage blocks; and a second switchelectrically connected between the controller and the storage blocks forselectively connecting the controller to another one of the storageblocks; wherein the first switch and the second switch are respectivelyconnected to different storage blocks.